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C/C++ Source or Header  |  2008-12-24  |  8.3 KB  |  258 lines
  1. /*
  2.  * This file is subject to the terms and conditions of the GNU General Public
  3.  * License.  See the file "COPYING" in the main directory of this archive
  4.  * for more details.
  5.  *
  6.  * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
  7.  */
  8. #ifndef _ASM_IA64_SN_PCI_TIOCP_H
  9. #define _ASM_IA64_SN_PCI_TIOCP_H
  10.  
  11. #define TIOCP_HOST_INTR_ADDR            0x003FFFFFFFFFFFFFUL
  12. #define TIOCP_PCI64_CMDTYPE_MEM         (0x1ull << 60)
  13. #define TIOCP_PCI64_CMDTYPE_MSI         (0x3ull << 60)
  14.  
  15.  
  16. /*****************************************************************************
  17.  *********************** TIOCP MMR structure mapping ***************************
  18.  *****************************************************************************/
  19.  
  20. struct tiocp{
  21.  
  22.     /* 0x000000-0x00FFFF -- Local Registers */
  23.  
  24.     /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
  25.     u64        cp_id;                /* 0x000000 */
  26.     u64        cp_stat;            /* 0x000008 */
  27.     u64        cp_err_upper;            /* 0x000010 */
  28.     u64        cp_err_lower;            /* 0x000018 */
  29.     #define cp_err cp_err_lower
  30.     u64        cp_control;            /* 0x000020 */
  31.     u64        cp_req_timeout;            /* 0x000028 */
  32.     u64        cp_intr_upper;            /* 0x000030 */
  33.     u64        cp_intr_lower;            /* 0x000038 */
  34.     #define cp_intr cp_intr_lower
  35.     u64        cp_err_cmdword;            /* 0x000040 */
  36.     u64        _pad_000048;            /* 0x000048 */
  37.     u64        cp_tflush;            /* 0x000050 */
  38.  
  39.     /* 0x000058-0x00007F -- Bridge-specific Configuration */
  40.     u64        cp_aux_err;            /* 0x000058 */
  41.     u64        cp_resp_upper;            /* 0x000060 */
  42.     u64        cp_resp_lower;            /* 0x000068 */
  43.     #define cp_resp cp_resp_lower
  44.     u64        cp_tst_pin_ctrl;        /* 0x000070 */
  45.     u64        cp_addr_lkerr;            /* 0x000078 */
  46.  
  47.     /* 0x000080-0x00008F -- PMU & MAP */
  48.     u64        cp_dir_map;            /* 0x000080 */
  49.     u64        _pad_000088;            /* 0x000088 */
  50.  
  51.     /* 0x000090-0x00009F -- SSRAM */
  52.     u64        cp_map_fault;            /* 0x000090 */
  53.     u64        _pad_000098;            /* 0x000098 */
  54.  
  55.     /* 0x0000A0-0x0000AF -- Arbitration */
  56.     u64        cp_arb;                /* 0x0000A0 */
  57.     u64        _pad_0000A8;            /* 0x0000A8 */
  58.  
  59.     /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
  60.     u64        cp_ate_parity_err;        /* 0x0000B0 */
  61.     u64        _pad_0000B8;            /* 0x0000B8 */
  62.  
  63.     /* 0x0000C0-0x0000FF -- PCI/GIO */
  64.     u64        cp_bus_timeout;            /* 0x0000C0 */
  65.     u64        cp_pci_cfg;            /* 0x0000C8 */
  66.     u64        cp_pci_err_upper;        /* 0x0000D0 */
  67.     u64        cp_pci_err_lower;        /* 0x0000D8 */
  68.     #define cp_pci_err cp_pci_err_lower
  69.     u64        _pad_0000E0[4];            /* 0x0000{E0..F8} */
  70.  
  71.     /* 0x000100-0x0001FF -- Interrupt */
  72.     u64        cp_int_status;            /* 0x000100 */
  73.     u64        cp_int_enable;            /* 0x000108 */
  74.     u64        cp_int_rst_stat;        /* 0x000110 */
  75.     u64        cp_int_mode;            /* 0x000118 */
  76.     u64        cp_int_device;            /* 0x000120 */
  77.     u64        cp_int_host_err;        /* 0x000128 */
  78.     u64        cp_int_addr[8];            /* 0x0001{30,,,68} */
  79.     u64        cp_err_int_view;        /* 0x000170 */
  80.     u64        cp_mult_int;            /* 0x000178 */
  81.     u64        cp_force_always[8];        /* 0x0001{80,,,B8} */
  82.     u64        cp_force_pin[8];        /* 0x0001{C0,,,F8} */
  83.  
  84.     /* 0x000200-0x000298 -- Device */
  85.     u64        cp_device[4];            /* 0x0002{00,,,18} */
  86.     u64        _pad_000220[4];            /* 0x0002{20,,,38} */
  87.     u64        cp_wr_req_buf[4];        /* 0x0002{40,,,58} */
  88.     u64        _pad_000260[4];            /* 0x0002{60,,,78} */
  89.     u64        cp_rrb_map[2];            /* 0x0002{80,,,88} */
  90.     #define cp_even_resp cp_rrb_map[0]            /* 0x000280 */
  91.     #define cp_odd_resp  cp_rrb_map[1]            /* 0x000288 */
  92.     u64        cp_resp_status;            /* 0x000290 */
  93.     u64        cp_resp_clear;            /* 0x000298 */
  94.  
  95.     u64        _pad_0002A0[12];        /* 0x0002{A0..F8} */
  96.  
  97.     /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
  98.     struct {
  99.     u64    upper;                /* 0x0003{00,,,F0} */
  100.     u64    lower;                /* 0x0003{08,,,F8} */
  101.     } cp_buf_addr_match[16];
  102.  
  103.     /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
  104.     struct {
  105.     u64    flush_w_touch;            /* 0x000{400,,,5C0} */
  106.     u64    flush_wo_touch;            /* 0x000{408,,,5C8} */
  107.     u64    inflight;            /* 0x000{410,,,5D0} */
  108.     u64    prefetch;            /* 0x000{418,,,5D8} */
  109.     u64    total_pci_retry;        /* 0x000{420,,,5E0} */
  110.     u64    max_pci_retry;            /* 0x000{428,,,5E8} */
  111.     u64    max_latency;            /* 0x000{430,,,5F0} */
  112.     u64    clear_all;            /* 0x000{438,,,5F8} */
  113.     } cp_buf_count[8];
  114.  
  115.  
  116.     /* 0x000600-0x0009FF -- PCI/X registers */
  117.     u64        cp_pcix_bus_err_addr;        /* 0x000600 */
  118.     u64        cp_pcix_bus_err_attr;        /* 0x000608 */
  119.     u64        cp_pcix_bus_err_data;        /* 0x000610 */
  120.     u64        cp_pcix_pio_split_addr;        /* 0x000618 */
  121.     u64        cp_pcix_pio_split_attr;        /* 0x000620 */
  122.     u64        cp_pcix_dma_req_err_attr;    /* 0x000628 */
  123.     u64        cp_pcix_dma_req_err_addr;    /* 0x000630 */
  124.     u64        cp_pcix_timeout;        /* 0x000638 */
  125.  
  126.     u64        _pad_000640[24];        /* 0x000{640,,,6F8} */
  127.  
  128.     /* 0x000700-0x000737 -- Debug Registers */
  129.     u64        cp_ct_debug_ctl;        /* 0x000700 */
  130.     u64        cp_br_debug_ctl;        /* 0x000708 */
  131.     u64        cp_mux3_debug_ctl;        /* 0x000710 */
  132.     u64        cp_mux4_debug_ctl;        /* 0x000718 */
  133.     u64        cp_mux5_debug_ctl;        /* 0x000720 */
  134.     u64        cp_mux6_debug_ctl;        /* 0x000728 */
  135.     u64        cp_mux7_debug_ctl;        /* 0x000730 */
  136.  
  137.     u64        _pad_000738[89];        /* 0x000{738,,,9F8} */
  138.  
  139.     /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
  140.     struct {
  141.     u64    cp_buf_addr;            /* 0x000{A00,,,AF0} */
  142.     u64    cp_buf_attr;            /* 0X000{A08,,,AF8} */
  143.     } cp_pcix_read_buf_64[16];
  144.  
  145.     struct {
  146.     u64    cp_buf_addr;            /* 0x000{B00,,,BE0} */
  147.     u64    cp_buf_attr;            /* 0x000{B08,,,BE8} */
  148.     u64    cp_buf_valid;            /* 0x000{B10,,,BF0} */
  149.     u64    __pad1;                /* 0x000{B18,,,BF8} */
  150.     } cp_pcix_write_buf_64[8];
  151.  
  152.     /* End of Local Registers -- Start of Address Map space */
  153.  
  154.     char    _pad_000c00[0x010000 - 0x000c00];
  155.  
  156.     /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
  157.     u64        cp_int_ate_ram[1024];        /* 0x010000-0x011FF8 */
  158.  
  159.     char    _pad_012000[0x14000 - 0x012000];
  160.  
  161.     /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
  162.     u64        cp_int_ate_ram_mp[1024];    /* 0x014000-0x015FF8 */
  163.  
  164.     char    _pad_016000[0x18000 - 0x016000];
  165.  
  166.     /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
  167.     u64        cp_wr_req_lower[256];        /* 0x18000 - 0x187F8 */
  168.     u64        cp_wr_req_upper[256];        /* 0x18800 - 0x18FF8 */
  169.     u64        cp_wr_req_parity[256];        /* 0x19000 - 0x197F8 */
  170.  
  171.     char    _pad_019800[0x1C000 - 0x019800];
  172.  
  173.     /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
  174.     u64        cp_rd_resp_lower[512];        /* 0x1C000 - 0x1CFF8 */
  175.     u64        cp_rd_resp_upper[512];        /* 0x1D000 - 0x1DFF8 */
  176.     u64        cp_rd_resp_parity[512];        /* 0x1E000 - 0x1EFF8 */
  177.  
  178.     char    _pad_01F000[0x20000 - 0x01F000];
  179.  
  180.     /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used)  */
  181.     char    _pad_020000[0x021000 - 0x20000];
  182.  
  183.     /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
  184.     union {
  185.     u8    c[0x1000 / 1];            /* 0x02{0000,,,7FFF} */
  186.     u16    s[0x1000 / 2];            /* 0x02{0000,,,7FFF} */
  187.     u32    l[0x1000 / 4];            /* 0x02{0000,,,7FFF} */
  188.     u64    d[0x1000 / 8];            /* 0x02{0000,,,7FFF} */
  189.     union {
  190.         u8    c[0x100 / 1];
  191.         u16    s[0x100 / 2];
  192.         u32    l[0x100 / 4];
  193.         u64    d[0x100 / 8];
  194.     } f[8];
  195.     } cp_type0_cfg_dev[7];                /* 0x02{1000,,,7FFF} */
  196.  
  197.     /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
  198.     union {
  199.     u8    c[0x1000 / 1];            /* 0x028000-0x029000 */
  200.     u16    s[0x1000 / 2];            /* 0x028000-0x029000 */
  201.     u32    l[0x1000 / 4];            /* 0x028000-0x029000 */
  202.     u64    d[0x1000 / 8];            /* 0x028000-0x029000 */
  203.     union {
  204.         u8    c[0x100 / 1];
  205.         u16    s[0x100 / 2];
  206.         u32    l[0x100 / 4];
  207.         u64    d[0x100 / 8];
  208.     } f[8];
  209.     } cp_type1_cfg;                    /* 0x028000-0x029000 */
  210.  
  211.     char        _pad_029000[0x030000-0x029000];
  212.  
  213.     /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
  214.     union {
  215.     u8    c[8 / 1];
  216.     u16    s[8 / 2];
  217.     u32    l[8 / 4];
  218.     u64    d[8 / 8];
  219.     } cp_pci_iack;                    /* 0x030000-0x030007 */
  220.  
  221.     char        _pad_030007[0x040000-0x030008];
  222.  
  223.     /* 0x040000-0x040007 -- PCIX Special Cycle */
  224.     union {
  225.     u8    c[8 / 1];
  226.     u16    s[8 / 2];
  227.     u32    l[8 / 4];
  228.     u64    d[8 / 8];
  229.     } cp_pcix_cycle;                    /* 0x040000-0x040007 */
  230.  
  231.     char        _pad_040007[0x200000-0x040008];
  232.  
  233.     /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
  234.     union {
  235.     u8    c[0x100000 / 1];
  236.     u16    s[0x100000 / 2];
  237.     u32    l[0x100000 / 4];
  238.     u64    d[0x100000 / 8];
  239.     } cp_devio_raw[6];                    /* 0x200000-0x7FFFFF */
  240.  
  241.     #define cp_devio(n)  cp_devio_raw[((n)<2)?(n*2):(n+2)]
  242.  
  243.     char        _pad_800000[0xA00000-0x800000];
  244.  
  245.     /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush  */
  246.     union {
  247.     u8    c[0x100000 / 1];
  248.     u16    s[0x100000 / 2];
  249.     u32    l[0x100000 / 4];
  250.     u64    d[0x100000 / 8];
  251.     } cp_devio_raw_flush[6];                /* 0xA00000-0xBFFFFF */
  252.  
  253.     #define cp_devio_flush(n)  cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
  254.  
  255. };
  256.  
  257. #endif     /* _ASM_IA64_SN_PCI_TIOCP_H */
  258.